1. Technical Field
The present invention relates to a semiconductor memory, and more particularly, to an apparatus for on-die termination of a semiconductor memory and a method of operating the same.
2. Related Art
In general, signals are transmitted through a bus line having a predetermined impedance. Therefore, when two bus lines having different impedances meet each other, some of the signals are lost. On-die termination (hereinafter, simply referred to as “ODT”) is a means of reducing signal loss by impedance matching of the two bus lines.
As shown in FIG. 1, an apparatus for on-die termination according to the related art includes a first ODT voltage generating unit 10 that outputs a first line voltage P_out by calibrating a power supply voltage VDDQ with the resistance ratio according to a first code (hereinafter, referred to as “Pcode<0:N>”); a first comparing unit 20 that compares the first line voltage P_out and a reference voltage Vref according to a first enable signal P_en so as to output a first comparison result signal Pcmp_out; a first register 30 that counts the Pcode<0:N> according to the first comparison result signal Pcmp_out; a second ODT voltage generating unit 40 that outputs a second line voltage N_out by calibrating a power supply voltage VDDQ with the resistance ratio according to the first code Pcode<0:N> and a second code (hereinafter, “Ncode<0:N>”; a second comparing unit 50 that compares the second line voltage N_out and the reference voltage Vref according to a second enable signal N_en so as to output a second comparison result signal Ncmp_out; and a second register 60 that counts the Ncode<0:N> according to the second comparison result signal Ncmp_out.
As shown in FIG. 2, the first ODT voltage generating unit 10 includes a plurality of transistors P0 to Pn that are respectively connected to power terminals VDDQ and are turned on according to the Pcode<0:N>; a plurality of resistors NR0 to NRn, each of which is connected between one of the plurality of transistors P0 to Pn; and an external resistor (hereinafter, referred to as “ZQ”).
The first ODT voltage generating unit 10 is modeled on a data input driver because the first ODT voltage generating unit 10 needs to have the same characteristics as those when data is normally input.
As shown in FIG. 3, the second ODT voltage generating unit 40 includes a plurality of transistors P0 to Pn that are connected to power terminals VDDQ and are turned on according to the Pcode<0:N>; a plurality of resistors NR0 to NRn, each of which is connected to each of the plurality of transistors P0 to Pn; a plurality of resistors PR0 to PRn that are connected to the plurality of resistors NR0 to NRn, respectively; and a plurality of transistors N0 to Nn, each of which is connected between one of the plurality of resistors PR0 to PRn and ground terminals VSSQ, and are turned on according to the Ncode<0:N>.
The second ODT voltage generating unit 40 is modeled on a data output driver because the second ODT voltage generating unit 40 needs to have the same characteristics as those when data is normally output.
The operation of the apparatus for on-die termination of the semiconductor memory according to the related art that has the above-described structure will be described below.
An initial value of the Pcode<0:N> that is previously set in the first register 30 is input to the first ODT voltage generating unit 10.
Then, the first ODT voltage generating unit 10 outputs a first line voltage P_out according to a resistance ratio between the resistors connected on the basis of the Pcode<0:N> and the ZQ.
Further, the first comparing unit 20 compares the first line voltage P_out and the reference voltage Vref according to the first enable signal P_en so as to output the first comparison result signal Pcmp_out according to the comparison.
The first register 30 counts and stores the Pcode<0:N> in a direction of increasing or decreasing the Pcode<0:N> according to the first comparison result signal Pcmp_out, and at the same time, the first register 30 outputs the counted Pcode<0:N> to the first ODT voltage generating unit 10.
The first ODT voltage generating unit 10 feeds back the first line voltage P_out based on the Pcode<0:N>, which is output from the first register 30, to the first comparing unit 20. As a result, the first comparing unit 20 repeats the above-described comparison operation and a corresponding operation of outputting the first comparison result signal Pcmp_out, thereby performing Pcode<0:N> calibration.
Meanwhile, an initial value of the Ncode<0:N> that is previously set in the second register 60, and the Pcode<0:N> whose calibration is completed in the first register 30 are input to the second ODT voltage generating unit 40.
The second ODT voltage generating unit 40 outputs the second line voltage N_out according to a resistance ratio between the resistors connected on the basis of the Pcode<0:N> and the resistors on the basis of the Ncode<0:N>.
Then, the second comparing unit 50 compares the second line voltage N_out and the reference voltage Vref according to the second enable signal N_en to thereby output the second comparison result signal Ncmp_out according to the comparison.
Then, the second register 60 counts and stores the Ncode<0:N> in a direction of increasing or decreasing the Ncode<0:N> according to the second comparison result signal Ncmp_out, and at the same time, the second register 60 outputs the counted Ncode<0:N> to the second ODT voltage generating unit 40.
At this time, the second ODT voltage generating unit 40 feeds back the second line voltage N_out according to the Ncode<0:N>, which is output from the second register 60, to the second comparing unit 50. As a result, the second comparing unit 50 repeats the above-described comparison operation and a corresponding operation of outputting the second comparison result signal Ncmp_out, thereby performing Ncode<0:N> calibration.
In the related art, during the Pcode<0:N> and the Ncode<0:N> calibration, the resistance value needs to be large when the first line voltage P_out and the second line voltage N_out are larger than the reference voltage Vref. Therefore, the value of the Pcode<0:N> is increased and the value of the Ncode<0:N> is decreased.
Further, when the difference between the resistance of the external resistor, ZQ, and the internal resistance is in an adjustable range, as code calibration is performed the increase and decrease of the Pcode<0:N> and the Ncode<0:N> is repeated in a predetermined range. When the code calibration is completed, the Pcode<0:N> and the Ncode<0:N> are set to values in a desired range.
Meanwhile, when the difference between the resistance of the ZQ and the internal resistance is not in the adjustable range, it is preferable that each of the Pcode<0:N> and the Ncode<0:N> be set to the maximum value or the minimum value in order to minimize resistance errors of data input and output drivers.
However, when the difference between the resistance of ZQ and the internal resistance is large, each of the Pcode<0:N> and the Ncode<0:N> repeatedly changes to the maximum value or the minimum value in a total variable range. Further, when the calibration is completed, the Pcode<0:N> and the Ncode<0:N> are set to values that are completely different from the desired values.